The present invention relates to a phase-locked loop circuit which is supplied with a random two-level code sequence derived from a clock pulse having a frequency f.sub.0 to generate a local clock pulse which is synchronous with the clock pulse in phase and frequency.
A phase-locked loop (PLL) is often needed in, for example, the timing circuit built into the receive section of a data modem, and the timing circuit built into the repeater which is used in pulse code modulation (PCM) communication systems. Recently, this type of PLL has also come to be used in the timing circuit of a device designed to retrive data from a digital recording medium.
A PLL of the type described is supplied with a random two-level code sequence and is provided with a different configuration from the ordinary PLL which serves to synchronize a local clock pulse with an externally supplied clock pulse. Specifically, where the input signal to the PLL is a clock pulse which is supplied from the outside, a phase difference between the input signal and the local clock pulse is detectable by, for example, taking the exclusive-OR of the input signal and the local clock pulse so that phase-locking may be accomplished by controlling a voltage controlled oscillator (VCO) responsive to the phase difference. However, where the input signal is a random two-level code sequence, the exclusive-OR output of the input signal and the local clock pulse fluctuates due to the statistical characteristic of the two-level code sequence, preventing an accurate phase difference from being detected.
Heretofore, various approaches have been proposed to eliminate the drawback which is particular to such an ordinary PLL as discussed. One approach is the PLL described by Ross C. Halgren in a paper entitled "Improved Acquisition in Phase-Locked Loops with Sawtooth Phase Detectors", IEEE Transactions on Communications, Vol. COM-30, No. 10, October 1982. However, the PLL scheme described in this paper has the disadvantage that when a pattern having a repetition frequency of f.sub.o /4 arrives, a signal whose frequency is one half the frequency of a local clock pulse necessarily appears at an output terminal to practically disable the control of the phase-locking.